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种子名称:
[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development
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视频
文件数目:
59个文件
文件大小:
1.93 GB
收录时间:
2021-4-28 19:21
已经下载:
3次
资源热度:
226
最近下载:
2025-1-5 12:02
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[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development.torrent
10. Xilinx Tools/1. Xilinx Tools Introduction.mp41.33MB
10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.mp436.93MB
10. Xilinx Tools/3. ISim VHDL Simulation Tool.mp44.68MB
10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.mp49.23MB
10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.mp41.79MB
11. Lab 1 - Full Adder/1. Introduction.mp45.68MB
11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp487.88MB
11. Lab 1 - Full Adder/3. BASYS 2 Full Adder Demonstration.mp431.9MB
11. Lab 1 - Full Adder/4. BASYS 2 Full Adder Solution.mp438.67MB
12. Lab 2 - Shift Register/1. Introduction.mp45.67MB
12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp446.87MB
12. Lab 2 - Shift Register/3. BASYS 2 Shift Register Demonstration.mp437.7MB
13. Lab 3 - Universal Shift Register/1. Introduction.mp45.07MB
13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp470.63MB
13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp462.3MB
13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp469.65MB
14. Lab 4 - 7 Segment Display/1. Introduction.mp46.09MB
14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp443.84MB
14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp445.39MB
15. Lab 5 - Counter/1. Introduction.mp43.7MB
15. Lab 5 - Counter/2. BASYS 3 Counter Demonstration.mp424.67MB
15. Lab 5 - Counter/3. BASYS 2 Counter Demonstration.mp431.44MB
16. Lab 6 - Multiplier/1. Introduction.mp47.57MB
16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4102.35MB
16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp461.87MB
17. Lab 7 - RC Servo/1. Introduction.mp421.31MB
17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp481.64MB
17. Lab 7 - RC Servo/3. BASYS 2 RC Servo Demonstration.mp425.91MB
2. Introduction/1. Introduction to the Course.mp435.18MB
2. Introduction/2. Introduction to VHDL.mp455.31MB
3. VHDL Data Types/1. Data Types Introduction.mp426.99MB
3. VHDL Data Types/2. Signals Variables Constants.mp441.58MB
3. VHDL Data Types/3. Unsigned Signed Data Types.mp447.51MB
3. VHDL Data Types/4. Standard Logic Vector Standard Logic.mp441.26MB
3. VHDL Data Types/5. Integer Boolean Data Types.mp434.61MB
3. VHDL Data Types/6. Initializing Values in VHDL.mp421.3MB
3. VHDL Data Types/7. Data Type Examples in VHDL Designs Part 1.mp414.9MB
3. VHDL Data Types/8. Data Type Examples in VHDL Designs Part 2.mp47.86MB
4. VHDL Syntax/2. If Statement Case Statement.mp476.21MB
4. VHDL Syntax/3. For Loop While Loop.mp470.39MB
4. VHDL Syntax/4. VHDL For Loop Example.mp48.07MB
4. VHDL Syntax/5. When Else Statement With Select When Statement.mp439.84MB
4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp455.72MB
4. VHDL Syntax/7. VHDL Syntax Design Example.mp49.58MB
5. VHDL Coding Structure/1. Organizing Your VHDL Designs.mp411.4MB
5. VHDL Coding Structure/2. VHDL Design Structure.mp460.82MB
5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp497.46MB
5. VHDL Coding Structure/4. Data Flow Architecture Example - Full Adder.mp49.71MB
5. VHDL Coding Structure/5. Behavioral Architecture Example - Full Adder.mp47.19MB
6. Test Bench/1. Test Benches Introduction.mp446.33MB
6. Test Bench/2. Test Bench Structure Walkthrough.mp48.18MB
6. Test Bench/3. Walkthrough of a Completed Test Bench.mp410.58MB
7. Implementing State Machines in VHDL/1. State Machine Introduction.mp431.36MB
8. FPGA Development Boards/2. BASYS 3 Board Overview.mp484.42MB
8. FPGA Development Boards/5. BASYS 2 Board.mp43.91MB
8. FPGA Development Boards/8. BASYS 2 Board Overview.mp437.81MB
9. Altera Tools/1. Altera Tools Introduction.mp42.47MB
9. Altera Tools/2. ModelSim VHDL Simulation Tool.mp46.24MB
9. Altera Tools/3. Quartus II FPGA Development Tool.mp44.3MB